The present invention relates to apparatus for controlling interruption requests in processor systems. More particularly, the present invention relates to an interruption control device for controlling interruption requests in a multiprocessor system having a plurality of interconnected processor elements.
As is well known in the art an interruption request is a computer instruction that instructs the processor of the computer to halt execution of a currently executing program and perform some other more important task associated with the device requesting the interruption. Typically, an interruption request is caused in a conventional processor system by a peripheral device such as an input/output (I/0) device actuating an interruption request line connected between the conventional processor system and the peripheral device.
In the conventional processor system a plurality of interruption request lines are provided so that a plurality of different interruptions may be caused by a plurality of different peripheral devices. The particular task performed by the conventional processor system is determined by the particular interruption request line being actuated. The identification of the source of an interruption request is made easy in the conventional processor system by simply identifying the interruption request line being actuated. As described above an interruption request line is connected between the conventional processor system and each peripheral device.
Identifying a particular task corresponding to a particular interruption request and the peripheral device or processor which caused the interruption request is more complicated in a multiprocessor system. A multiprocessor system includes a plurality of interconnected processor elements and a plurality of peripheral devices each connected to one or more of the processor elements. Each of the processor elements and each of the peripheral devices may cause an interruption request in at least one of the processor elements.
A simple way to accomplish the identification of the particular interruption request to be performed and the peripheral device or processor element causing the interruption request in a multiprocessor system is to electrically connect an interruption request line between each peripheral device and each processor element of the multiprocessor system. This arrangement permits each peripheral device or processor element to initiate an interruption request in any one of the processor elements of the multiprocessor system.
Although the above-described apparatus permits each processor element to receive an interruption request from any one of the peripheral devices or any one of the other processor elements, the apparatus suffers from the disadvantage of having numerous interconnecting wires between the processor elements of the multiprocessor system and the peripheral devices. Such an arrangement becomes extremely cumbersome as the multiprocessor system grows in size by the addition of new processor elements and peripheral devices.
Apparatus has been proposed for reducing the number of interruption request lines in the above-described arrangement in Japanese Application No. 163948/88. The apparatus as disclosed in Japanese Application No. 163948/88 provides a single interruption request line connected to all of the processor elements of the multiprocessor system. The single interruption request line designates a processor element to which an interrupt is to be requested by addressing and storing information in a specific memory space of the memory of the processor element to be interrupted. In accordance with the apparatus described in Japanese Application No. 163948/88 a device, connected between each of the I/O devices or processor elements and the single interruption request line, is provided for performing the addressing and storing operation described above.
Thus, in the apparatus disclosed by Japanese Application No. 163948/88, when an interruption request is generated by one of the I/O devices an address is simultaneously output by the device to the memory of one of the processor elements of the multiprocessor system corresponding to the interruption request via the single interruption request line. The address generated by the device addresses a particular memory space in the memory of the processor element corresponding to the requested interruption.
Although the above-described apparatus disclosed in Japanese Application No. 163948/88 reduces the number of interruption request lines connected between the processor elements of the multiprocessor system and the peripheral devices, the apparatus disclosed by Japanese Application No. 163948/88 suffers from the disadvantage of reducing the throughput of interruption requests between the processor elements of the multiprocessor system and the peripheral devices. In the apparatus disclosed by Japanese Application No. 163948/88 only one interruption request at a time can be handled by the device being that an address must be generated which is output on the single interruption request line connected to each of the processor elements of the multiprocessor system.
Therefore, based on the above, there is not provided a conventional system for generating an interruption request that reduces the amount of hardware needed to implement effective interruption control where a particular interruption request and the source of interruption request is identified to a processor element in a multiprocessor system.
Further, there is not provided a conventional system which does not limit the throughput of interruption requests to different processor elements in a multiprocessor system thereby permitting the efficient control of simultaneous and sequential interruption requests.